A Fully Integrated CMOS Clock Data Recovery IC for OC-192 Applications;

Copyright (c) 2007 IEEE. Personal use of this material is permitted. However, permission to use this material for any other purposes must be obtained from the IEEE by sending an email to [email protected]. 1 Abstract— In this paper, a fully integrated OC-192 clock-data recovery (CDR) architecture in standard 0.18 m CMOS is described. The proposed architecture integrates the typically large off-chip filter capacitor by using two feed-forward paths configuration to generate zero and pole and satisfies SONET jitter requirements with a total power dissipation (including the buffers) of 290mW. The measured RMS jitter of the recovered data is 0.74ps with a bit-error rate (BER) less than 10 when the input PRBS data pattern has a pattern length of 2-1 and a total horizontal eye closure of 0.54 UIpp due to the added ISI distortion by passing data through 9 inches FR4 PCB trace. The chip exceeds SONET OC-192 jitter tolerance mask, and high frequency jitter tolerance is over 0.31 UIpp by applying PRBS data with a pattern length of 2-1.